1. Technological Field of the Invention
The present invention relates to the field of manufacturing products, such as semiconductor chips, and more particularly, to a method and apparatus for detecting systematic pattern defects related to the manufacturing process.
2. Description of Related Art
The manufacturing process of wafers containing semiconductor devices comprises a number of discrete processing steps to produce a semiconductor circuit device from raw semiconductor material. The starting substrate is usually a slice of single crystal silicon referred to as a wafer (FIG. 1) 100 on which a plurality of dies 104 are formed by a semiconductor processing method. There are any number of various semiconductor processing methods, such as etching, epitaxy, oxidation, deposition (e.g., chemical vapor or physical), sputtering, diffusion, ion implantation, chemical mechanical polishing, and lithography, each of which typically has multiple steps. The semiconductor processing methods are used to form regular arrays (FIG. 2A) 106 of integrated circuits. FIG. 2A illustrates that the circuits are typically created in a die, such as 104a, from a plurality of conductive paths 109 which together form a layout structure 108a. These paths may be arranged in regular repeating arrays, as in for example the cache memory of a microprocessor or the core of a memory device, or randomly within the die, as in the primary logic areas of a microprocessor or the controlling logic of a memory device, depending upon their function in the circuit. Layout structures 108a, 108a', 108a" are shown in FIG. 2A only as partial views of the exemplary conductive paths 109 that comprise a randomly laid out area of a much more complicated circuit configuration (not shown). The layout structures 108a may be considered a cell, for purposes of discussion.
Each particular conductive path 109 of layout structure 108a affected differently by the various processing methods. Taking the etching semiconductor method as an example, it is widely known that different design layout structures (generally referred to with numeral 108) have different sensitivities to local etch/polish/masking steps, as well as to variances in the loading and proximity of the structures (i.e. paths 109) to one another. These sensitivities may result in unintended processing errors which produce unwanted effects. Examples of these unwanted effects include a bridge 110 (FIG. 2B) between paths 109 of layout structure 108b that are intended to be separate, an open area 112 (FIG. 2C) between paths 109 of layout structure 108c which are intended to be contiguous, a differential layer thickness (not shown) due to non-uniform polish, an under-etched contact (not shown), or any number of unwanted effects which are hereinafter referred to as "systematic pattern errors".
Although there is a general understanding that areas densely packed with layout structures will, for example, etch differently than loosely packed areas, there is currently no automated means for detecting which areas are most susceptible to systematic pattern errors. This is especially a problem in inherently random structures where the density of layout structures varies such that no particular area can be identified as more problematic than another. This problem is exacerbated by the current state of the art in layout methodology which allows for automated placement of paths 109 (and spaces between the paths) of layout structures 108 to be accomplished using predetermined design rules. If a particular structure 108 which tends to be problematic due to its location next to other structures is not explicitly excluded from a design rule, unwanted failures (e.g., shorts or unconnected contacts) might occur during the actual production of the semiconductor wafer. Further complicating the matter is the fact that the layout engineers may not be aware of the existence of such problems due to the automated layout process mentioned above.
Currently, systematic pattern errors in layout structures randomly placed according to automated design rules can only be found by manual optical inspection or examination of electrical performance of test structures in these areas. Standard automated wafer inspection tools which are useful for detecting non-systematic defects, such as particulate defects or non-repeating improperly formed patterns, cannot be used to find repeating failures like bridge 110 (FIG. 2B).
Turning to FIG. 2B, for example, two paths 109 of layout structure 108a can be randomly laid out by automated design rules repeatedly across dies 104a, 104b, and 104c. If the actual manufacturing process used provides the intended result, the structure will look like 108a. However, if there are variances in the processing method, such as a slightly longer etch time, bridge 110 might be formed to yield structure 108b which would be located in each die 104a, 104b, and 104c. Alternatively, FIG. 2C illustrates the results of an attempt to avoid creating bridge 110. Slightly less etch time was used in FIG. 2C as compared to that used in FIGS. 2A and 2B, but open area 112 is formed to yield structure 108c.
If the automated design rules designed a die with thousands of layout structures intended to be like structure 108a, but the die also included hundreds of thousands of other structures, it is very difficult to determine which of the structures 108a caused a failure. Furthermore, all structures 108a may have errors only when placed adjacent to certain structures, but the automated design rules may have specified this type of failing combination which repeats itself in random locations all across die 104a.
Current state of the art defect inspection tools typically use two image subtraction methods for inspecting areas of integrated circuits. The first, called cell-to-cell, is used when the area being inspected can be subdivided into a small area which contains identical structures 108a laid out in repetitive array 106 such as the core of a memory device or the cache of a microprocessor device. The second, called die-to-die, is used when the area being inspected does not repeat over significant distances and thus cannot be subdivided into identical cells so the entire die 104a is compared to identical dies 104b, 104c, 104d. Die-to-die defect detection is typically used to find random, non-repeating defects.
In cell-to-cell mode, an image of array 106 of the repeating cell structure 108a is acquired and compared to another image of structure 108a in array 106 in a nominally identical neighboring region. These images are compared, and where they differ, the inspection tool identifies that location as a defect. In the case of FIG. 2A, no defect would be detected by this method because no errors exist when comparing the images of identical structures 108a. However, the cell-to-cell mode would detect errors when comparing images of the structures 108a, 108b, 108c in FIG. 2B if those structures were contained in array 106. Specifically, when comparing structure 108a with 108b and 108c, cell-to-cell mode would detect bridge 110 and open area 112. This cell-to-cell defect detection process continues as the entire repeating array 106 is stepped through, comparing each cell to its nearest neighbor and assigning defect locations.
In die-to-die mode, an image of the entire die 104a, or subset thereof, is compared to a nominally identical image in the neighboring die 104b. The same type of image comparison is performed as in the cell-to-cell mode. (smaller portions "swaths" are almost always used to cut down on the memory overhead.)
The two defect detection methods discussed immediately above can be seen to be scaled versions of one another with the requirement that the two images being compared must be substantively identical. Both techniques are useful for detecting particulates, scratches and processing-induced defects like missing features, residual photoresist etc. However, any feature which is present in both images being compared will not be detected, as only differences are detectable. Layout specific process induced defects (e.g., repeating systematic pattern errors) fall into this category.
One of the problems with the existing defect inspection methods is that repeating systematic pattern errors are not detected. This may occur, for example, because image subtraction performed according to either the cell-to-cell or die-to-die methodologies results in no difference between compared images. Without using manual optical inspection or examination of electrical performance of test structures in these areas, the repeating systematic pattern errors remain undetected.